(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming opening for metal contacts and Vias.
(2) Description of Prior Art
The integrated circuit (IC) industry continues relentlessly towards smaller device geometries and greater circuit densities. This trend is made possible by the development of new manufacturing techniques as well as innovative improvements of existing procedures thereby extending their utility further towards miniaturization and higher density. The benefits and rewards of these efforts in very large scale integrated circuit(VLSIC) technology development are extraordinary. Not only are the ICs of today cheaper to produce, they continue to reward the end user with improved reliability and increased speed.
One such discipline wherein the limits of technology are constantly tested is the formation of openings in insulative layers wherein contacts to subjacent semiconductive elements are made. These openings generally represent the smallest photolithographically defined features of the integrated circuit. The openings are typically formed by reactive ion etching (RIE) through the insulative layer using a patterned photoresist mask. RIE is a well known anisotropic etching technique which can provide deep vertical openings having high aspect ratios. The aspect ratio in this regard is defined as the depth of the opening divided by its width.
The steady evolution in the capabilities of advanced optical lithography systems using 248 nm. wavelength laser light has made the achievement of 230 nm. resolution possible. In spite of the improvements in lens quality, however, these resolutions come at the expense of very small depth of focus. The resolution, 2b, according to Rayleigh's criterion may be expressed by: ##EQU1## where 2b is smallest distance between two resolved points. .lambda. is the wavelength of the light and NA is the numerical aperture of the lens (see Wolf, S. and Tauber, R. N., "Silicon Processing for the VLSI Era", Vol. 1, Lattice Press, Sunset Beach, Calif., (1986), p463). In order to achieve a resolution of 250 nm. using 248 nm. wavelength light source, a numerical aperture of about 0.65 is required. The constant K.sub.1, is typically about 0.6 but can be further reduced by the use of techniques such as off-axis illumination, phase shifting masks (PSM), and optical proximity correction (OPC), thereby further improving the resolution.
The depth of focus a, may be expressed by: ##EQU2## It can readily be seen that the depth of focus decreases rapidly at short wavelengths and high numerical apertures. In order to achieve the above resolution, a depth of focus of only 587 nm. must be contended with.
The formation of contact openings for sub-quarter micron IC technology requires such a fine photolithographic resolution. The narrow depth of focus dictates the use of photoresist layer having a thickness no greater than, and preferably smaller than the depth of focus. In the conventional process, the photoresist layer must be sufficiently thick to endure the etching period wherein the RIE of the insulative layer takes place. The insulative layer is typically between about 6,000 and 20,000 Angstroms thick. The photoresist materials used in deep-Ultraviolet (DUV) photolithography do not afford a sufficiently high etch rate selectivity to permit the use of thin enough photoresist layers. In order to etch the contact openings through the insulative layer, typically 8,000 to 20,000 .ANG. of photoresist is required. This exceeds the amount permitted to achieve the required resolution.
The method of this invention utilizes a hard mask which is deposited over the insulative layer. This mask is then patterned using a thin photoresist layer. Then, using the residual photoresist and the hard mask, the insulative layer is etched. The hard mask affords a high etch rate selectivity for the RIE of the insulative layer and therefore can be made relatively thin. Consequently the thickness of the photoresist layer required to pattern the hard mask is also reduced, placing it well within the limits required to achieve optimum photolithographic resolution.
Hardmasks have been used in other etching applications. Douglas et.al., U.S. Pat. No. 4,654,112 uses an intermediate hardmask of plasma enhanced chemical vapor deposited (PECVD) silicon to etch an insulative layer using nitrogen trifluoride plus oxygen chemistry. The NF.sub.3 /O.sub.2 combination had a high SiO.sub.2 /Si selectivity and did not produce residues as did a conventional fluorocarbon with O.sub.2 combination. The NF.sub.3 /O.sub.2 chemistry is deleterious to organic materials such as photoresist so a photoresist mask could not be used for the oxide etching. Instead a hardmask was formed by patterning a layer of PECVD silicon over the oxide layer. The silicon hardmask was able to withstand the corrosiveness of the NF.sub.3 /O.sub.2 atmosphere.
Likewise Srodes, et.al., U.S. Pat. No. 4,915,779 utilized a material such as silicon oxide to protect the surface of an aluminum alloy layer during the patterning of the aluminum with CF.sub.4, O.sub.2, BCl.sub.3, and Cl.sub.2. The photoresist layer used to pattern the hardmask was between 1.2 t o 2.5 microns thick.
Jillie, et.al., U.S. Pat. No. 4,808,259 performs an RIE through a stack wherein the photoresist pattern resides upon an upper layer, part of which may be expendable after the photoresist is depleted. However, this is not a true hardmask technique.